Publications
- P. V. Nikitin, V. Jandhyala, D. White, N. Champagne, J. Rockway Jr., C.-J. R. Shi,
C. Yang, Y. Wang, G. Ouyang, R. Sharpe, and J. Rockway Sr., "Modeling mixed
circuit-electromagnetic effects in electronic design flow", IEEE
ISQED conference, San Jose, March 2004
- S. Bhattacharya, N. Jangkrajarng, R. Hartono and R. Shi,
"Multiple specifications radio frequency
integrated
circuit design with automatic template-driven layout retargeting",
ASP-DAC Asia South Pacific Design Automation Conference,
Jan. 2004 Yokohama, Japan
- S. Bhattacharya, N. Jangkrajarng, R. Hartono and R. Shi,
"Hierarchical extraction and
verification of symmetry
constraints for analog layout automation",
ASP-DAC Asia South Pacific Design Automation Conference,
Jan. 2004, Yokohama, Japan
- B. Hu, G. Shi, and R. Shi,
"Symbolic model order reduction",
IEEE BMAS conference, Oct. 2003, San Jose, CA
- P. Nikitin, E. Normark, and R. Shi,
"Distributed electrothermal modeling in VHDL-AMS",
IEEE BMAS conference, Oct. 2003, San Jose, CA
- P. Nikitin, W. Yam, and R. Shi,
"Parametric equivalent circuit extraction for VLSI structures",
IFIP International VLSI-SoC Conference, Dec. 2003, Darmstadt,
Germany
- Z. Li and R. Shi, "SILCA:
Fast-yet-accurate
time-domain simulation
of VLSI circuits with strong parasitic coupling effects",
IEEE/ACM International Conference on Computer-Aided Design,
Nov. 2003, San Jose, CA
- L. Yang and R. Shi,Frosty: a fast
hierarchy extractor for
industrial CMOS circuits", IEEE/ACM International
Conference on Computer-Aided Design, Nov. 2003, San Jose, CA
- L. Zhou, B. Hu, B. Wan and R. Shi, "Rapid BSIM model
implementation
with VHDL-AMS/Verliog-AMS and MCAST Compact Model Compiler",
IEEE Systems-on-Chip Conference, Sept. 2003,
Portland, OR
- P. Nikitin, C.-J. R. Shi, and B. Wan, "Modeling
partial
differential equations
in VHDL-AMS", IEEE Systems-on-Chip
Conference,
Sept. 2003, Portland, OR
- B. Wan, B. Hu, L. Zhou and R.
Shi, "MCAST: An
abstract-syntax-tree
based model compiler for circuit simulation", IEEE
Custom Integrated Circuits Conference, Sept 2003, San Jose, CA
- N. Jangkrajarng, S. Bhattacharya, R. Hartono,
and R. Shi, "IPRAIL - Intellectual Property
Reuse-based Analog IC Layout Automation",
special issue of "Integration, the VLSI journal" published by
Elsevier science
- N. Jangkrajarng, S. Bhattacharya, R. Hartono, and R. Shi, "Automatic analog layout
retargeting for new processes and device sizes", ISCAS, May 2003, Bangkok,
Thailand
- S. Bhattacharya and R. Shi, "Concurrent
logic and interconnect delay estimation of MOS
circuits
by mixed algebraic and Boolean symbolic analysis", ISCAS, May 2003, Bangkok,
Thailand
- Yong Wang, D. Gope, V. Jandhyala, and R Shi,
"Integral equation-based coupled electromagnetic
circuit simulation in the frequency
domain", IEEE Antennas and Propagation Society International Symposium, June 2003,
Columbus, OH
- A. Manthe, Z. Li, and R. Shi, "Symbolic
analysis of analog circuits with hard
nonlinearity", IEEE Design Automation Conference, June 2003