| Model Description | This lumped-charge LDMOS model provides a physically-based compact model for LDMOS IC design. It is designed to replace other models (like the modified BSIM3) not specifically designed for the LDMOS structure. The model includes moderate inversion and effects of high field on carrier mobility. |
| Model Parameters | The model contains 38 parameters. Please see the model source code for the list of parameters. |
| Performance Level: | ACCURATE |
| Quality Classification: | 2B
This model has been extensively used. As in most compact models for IC design, parameter extraction is based on process and structure information |
| Original Support for Model Development | CDADIC, 1996-98 |
| Documentation | This LDMOS model is described in the MSEE Thesis
of Yeshwant Subramanian at the University of Washington, "Development of
Compact Vertical and Lateral DMOS Models", August 1998.
Simulation data is also given in Yeshwant Subramanian, P. O. Lauritzen, K.R. Green, "Two Lumped-Charge Based Power MOSFET Models", Proc. of IEEE Workshop on Computers in Power Electronics, Como, Italy, July1998, pp. 1-10. The model equations are also given in Yeshwant Subramanian, P. O. Lauritzen, K.R. Green, "A compact model for an IC lateral diffused MOSFET using the lumped-charge methodology", Proc. of MSM'99, Modeling and Simulations of Microsystems, San Juan, Puert o Rico, USA, April 1999 |
| Download Model Source Code | Model
1
This model is described in the thesis and the above papers. Model 2
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