Silicon Systems Research Lab

Professor C.-J. Richard Shi

Chip Gallery

Programmable deep learning accelerator iFPNA in 28nm CMOS supporting any CNN/LSTM/GRU [2017]
TI SAR ADC & low threshold low power comparator, 65nm [2016]
Deep learning processor OCEAN with 8 LSTM/GRU accelerators in 65nm CMOS [2016]

About Us


The UW Silicon Systems Research Lab is currently focusing on energy-efficient nanometer integrated circuit and system design for sensing, learning, communication, and computing. In collaboration with Professor Michael Taylor, we are building in the industry start-of-art 14nm FinFET process

  • RISC-V processor controlled deep learning accelerators
  • Gbps high-speed interfaces
  • Efficient mixed-signal Internet-of Thing sensing circuits

for enabling AI-infused edges and clouds. We are particularly embracing the open-source hardware and software initiative for system innovation.

Our lab has previously worked intensively on methodologies and tools to automate the design and verification of mixed-signal integrated circuits, resulting in commercial EDA tools and standards that have been used in production by the semiconductor industry. For a snapshot of our prior research, check out these publications.

SSRL welcomes undergraduate and graduate students to join our research endeavor to shape the future of our society with better productivity, qualify of life, and equal opportunity for all.

  • 07/03/2018 Our paper is accepted by ECCV 2018.
  • 05/31/2018 Our OCEAN journal paper is accepted by JETCAS.
  • 05/20/2018 Our iFPNA circuit design paper is accepted by ESSCIRC 2018.
  • 02/20/2018 Our iFPNA compilation work is accepted by DAC 2018.
  • 01/18/2018 Our PAM-8 Serdes paper is accepted by ISCAS 2018.
  • 12/01/2017 Our iFPNA circuit design is accepted to be presented in the ISSCC 2018 SRP session.
  • 06/01/2017 Our sub-nW comparator paper appears in IEEE TCAS-I.
  • 05/27/2017 Our OCEAN RNN design is presented at ESSCIRC 2017.