| Model Description | This model is an intermediate diode model based on the standard SPICE diode and the Basic Diode with the addition of voltage-dependent reverse recovery. The instantaneous diode reverse voltage modulates the diode current during reverse recovery. |
| Model Parameters | Model parameters are the same as those of the standard SPICE diode model with the addition of carrier lifetime "Tau" and the voltage "PhiB" needed to deplete the internal lightly doped region by one diffusion length. The standard SPICE diode includes o nly a diffusion transit time parameter "TT". Both "TT" and "Tau" are required for reverse recovery. Typically, "PhiB" is of similar magnitude as the diode breakdown voltage. |
| Performance Level: | INTERMEDIATE |
| Quality Classification: | 1B Only limited testing has been performed. Parameter extraction is available. |
| Original Support for Model Development | CDADIC, 1997-98 |
| Documentation | Jiahui Wu, EE 532 class project
at
the University
of Washington, May 1997.
Yafei Bi, "Compact Modeling of Power Bipolar Transistor in LDMOS Structures", MSEE Thesis, University of Washington, December 1998 |
| Download Model Source Code | Saber
MAST HDL model Verilog-A HDL model |