Analog Fault Simulation and Test Generation
PI |
Students |
Sponsors |
Publications
Principal Investigator
Participating Students:
Michael Tian (Now with Cadence Design Systems)
Nihal Godambe (Now with Motorola)
Guoyong Shi (Now a Professor with Shanghai Jiao Tong University)
Sponsors:
DARPA EP&I Program (1996-2001)
Publications
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C.-J. R. Shi, M. Tian and G. Shi, " Nonlinear DC fault simulation: one-step relaxation and adaptive simulation continuation"
IEEE Trans. on Computer-Aided Design, accepted.
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C.-J. Shi, Fault Simulation, Chapter 3 and pp. 55-92 in Analog
and Mixed-Signal Test, Bapiraju Vinnakota (ed.),
Prentice-Hall, 1998.
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C.-J. Shi and W. Tian, Simulation and Sensitivity of Linear(ized) Analog
Circuits under Parameter Variations, Chapter 44 and pp. 540-551 in
VLSI: Integrated Systems on Silicon, Ricardo Reis and Luc Claesen
(eds.), Chapman & Hall, 1997.
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C.-J. Shi and W. Tian,
``Simulation and sensitivity of linear analog
circuits under parameter variations by robust interval analysis",
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 4, no. 3, July 1999.
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N. Godambe and C.-J. Shi, ``Behavioral-level noise modeling and jitter
simulation of phase-locked loops with faults using VHDL-AMS",
Journal
of Electronic Testing: Theory and Applications (JETTA), vol. 9, no.
3, August 1998.
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L. Yang, C. Wakayama, and C.-J. R. Shi, "Noise-aware behavioral modeling of a fractional-N frequency synthesizer",
Proc. Great Lake Symp. on VLSI, April 2005 (accepted and to appear)
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T. Pi and C.-J. Shi,
``Analog testability analysis by determinant-decision
diagrams-based symbolic analysis",
accepted by
Asia and South Pacific Design Automation Conference (ASP-DAC'99),
Hong Kong, Jan. 2000.
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C.-J. Shi and W. Tian, ``Automatic test generation for linear(ized) analog
circuits under parameter variations", pp. 501-506 in Proc. Asia and
South Pacific Design Automation Conference (ASP-DAC'98), Tokyo, Japan,
Feb. 10-13, 1998. (Nominated by the program committee for the Best Paper
Award.)
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W. Tian and C.-J. Shi, ``Efficient DC fault simulation of nonlinear analog
circuits", pp. 899-904 in Proc. Design, Automation and Test in Europe
Conference and Exhibition (DATE'98), Paris, France, Feb. 23-26, 1998.
(merged EuroDAC and ED&TC conferences.) ( 122 out of 448 submissions
were selected)
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W. Tian and C.-J. Shi, ``Worst-case analysis of linear analog circuits
using sensitivity bands", pp. 110-113 in Proc. IEEE International Symposium
on Circuits and Systems, vol. VI, 1998.
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W. Tian and C.-J. Shi, ``Nonlinear Analog DC Fault Simulation by One-Step
Relaxation", pp. 126-131 in Proc. 16th IEEE VLSI Test Symposium,
Hyatt Regency Monterey, Monterey, CA, April 26-30, 1998.
(Best Paper Award.)
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C.-J. Shi, ``Block-level fault isolation using partition theory and logic
minimization techniques", pp. 319-324 in Proc. Asia and South Pacific
Design Automation Conference (ASP-DAC'97), Chiba, Japan, Jan. 28-31,
1997.
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N. Godambe and C.-J. Shi, ``Behavioral-level noise modeling and jitter
simulation of phase-locked loops with faults using VHDL-AMS", pp. 177--183
in Proc. IEEE VLSI Test Symp. (VTS'97), Monterey, CA, April 27 -
30, 1997 (62 out of 178 submissions were accepted).
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W. Tian and C.-J. Shi, ``Rapid frequency-domain analog fault simulation
under parameter tolerances", pp. 275 -- 280 in Proc. IEEE/ACM Design
Automation Conference (DAC'97), Anaheim, CA, June 9-13, 1997 (139
out of 389 submissions accepted).
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C.-J. Shi and W. Tian, ``Simulation and sensitivitity of linear(ized) analog
circuits under parameter variations", in Proc. 9th IFIP International
Conference on Very Large Scale Integration (VLSI'97), Gramado, BRAZIL,
August 26-29, 1997.
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C.-J. Shi, ``Block-level fault isolation for mixed-signal multichip modules
under parameter varations", IEEE/IMAPS MCM Test IV Workshop, Napa
Valley, California, Sept. 14 - 17, 1997.
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C.-J. Shi, ``Fault isolation for mixed-signal multichip modules", in IEEE
MCM Test II Workshop, Napa Valley, California, Sept. 15 - 18, 1996.
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C.-J. Shi and N. Godambe, ``Behavioral fault modeling and simulation of
phase-locked loops using a VHDL-A like language", pp. 245-250 in Proc.
IEEE International ASIC Conference & Exhibit (ASIC'96), Rochester,
N.Y., September 23-27, 1996. (Acceptance Ratio: 0.5)