Publications of C.-J. Richard Shi

Thesis | Contribution to Books | Special Issues | Journal Papers | Conference Papers

Publications Sorted by Years

Notes: (1) Publications by IEEE, ACM, and Kluwer are copyrighted by the respective organizations. Reproduction of any material contained in these publications requires explicit permission by the publisher. (2) Extended versions of conference papers marked by * appeared later in journals.

Thesis:

Book Chapters:

  1. C.-J. Shi, Fault Simulation, Chapter 3 and pp. 55-92 in Analog and Mixed-Signal Test, Bapiraju Vinnakota (ed.), Prentice-Hall, 1998.
  2. C.-J. Shi and W. Tian, Simulation and Sensitivity of Linear(ized) Analog Circuits under Parameter Variations, Chapter 44 and pp. 540-551 in VLSI: Integrated Systems on Silicon, Ricardo Reis and Luc Claesen (eds.), Chapman & Hall, 1997.
  3.  C.-J. Shi and A. Vachoux, VHDL-AMS Design Objectives and Rationale, Chapter 1 and pp. 1-30 in Modeling in Analog Design, vol. 2 in Series Current Issues in Electronic Modeling (CIEM), Jean-Michel Berge, Oz Levia and Jacques Rouillard (eds.), Kluwer Academic Publishers, 1995.
  4.  C.-J. Shi, Constrained Via Minimization and Signed Hypergraph Partitioning, pp. 337-356 in Algorithmic Aspects of VLSI Layouts, D. T. Lee and M. Sarrafzadeh (eds.), World Scientific Publishing Company, 1993.
  5. W.-Q. Zhao and C.-J. Shi, Schematic Capture and Automatic Generation of Circuit Diagrams, Chapter 1 and pp. 1-27 in Computer Aided Design of VLSI Circuits: Theory and Methods, P. Tan (ed.), Fudan University Press, 1990.

Special Issues:

  1. C.-J. R. Shi and W. H. Kao (Guest Editors), IEEE Trans. Circuits and Systems --- II: Analog and Digital Signal Processing, Special Issue on Behavioral Modeling and Simulaiton of Mixed-Signal/Mixed-Technology Systems, vol. 46, no. 10, Oct. 1999.

Journal Papers

  1. L. Zhang, N. Jangkrajarng, S. Bhattacharya, and C.-J. R. Shi, "Parasitic-aware optimization and retargeting of analog layouts: a symbolic template approach", IEEE Trans. on Computer-Aided Design, 2007.
  2. B. Hu and C.-J. R. Shi, "Simulation of closely-related dynamic nonlinear systems with application to process-voltage-temperature corner analysis", IEEE Trans. on Computer-Aided Design, 2007.
  3. L. Zhou, C. Wakayama, and C.-J. R. Shi, "CASCADE: A standard super-cell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large scale integrated circuits", IEEE Trans. on Computer-Aided Design, vol. 26, no. 7, July 2007.
  4. P. Nikitin, and C.-J. R. Shi, "VHDL-AMS based modeling and simulation of mixed-technology microsystems: A tutorial", Integration, the VLSI Journal, vol. 40, no. 3, pp. 261-273, April 2007.
  5. Z. Li and C.-J. R. Shi, "A quasi-Newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings", IEEE Trans. on Computer-Aided Design, vol. 25, no. 12, pp. 2867-2881, Dec. 2006.
  6. C.-J. R. Shi, M. Tian and G. Shi, "Nonlinear DC fault simulation: one-step relaxation and adaptive simulation continuation", IEEE Trans. on Computer-Aided Design, vol. 25, no. 7, pp. 1392-1400, July 2006.
  7. G. Shi, B. Hu, and C.-J. R. Shi, "On symbolic model order reduction", IEEE Trans. on Computer-Aided Design, vol. 25, no. 7, pp. 1257-1272, July 2006.
  8. Z. Li and C.-J. R. Shi, "SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain simulation of VLSI circuits with strong parasitic couplings", IEEE Trans. on Computer-Aided Design, vol. 25, no. 6, pp. 1087-1103, June 2006.
  9. S. Bhattacharya, N. Jangkrajarng, and C.-J. R. Shi, "Multi-level symmetry constraint generation for retargeting large analog layouts" , IEEE Trans. on Computer-Aided Design, vol. 25, no. 5, pp. 945-960, June 2006.
  10. L. Yang, H. Liu, and C.-J. R. Shi, "Construction and FPGA implementation of low-error-floor multi-rate low-density parity-check code decoders", IEEE Trans. on Circuits and Systems-I, vol. 53, no. 4, pp. 892-904, April 2006.
  11. L. Yang and C-J. R. Shi, "FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits," Integration, the VLSI Journal, vol. 39, no. 2, Dec. 2005. (Science Direct: Top 25 hottest article in the journal).
  12. B. Hu, C. Wakatama, L. Zhou and C.-J. R. Shi, "Rapid implementation of semiconductor device models in SPICE with MCAST compact model compiler", IEEE Circuits and Devices, vol. 21, no. 4, July 2005.
  13. G. Shi and C.-J. R. Shi, "Model order reduction by dominant subspace projection: error bounds, subspace approximation and circuit applications," IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 52, no. 5, pp. 975-993, May 2005.
  14. B. Wan and C.-J. R. Shi, "Hierarchical multi-dimensional table lookup for model-compiler-based circuit simulation," IEE Proceedings on Computers and Digital Techniques, vol. 152, no. 1, pp. 39-44, Jan. 2005.
  15. Z. Li, R. Suravarapu, K. Mayaram and C.-J. R. Shi, "Automatic extraction of layout-dependent substrate effects for RF MOSFET modeling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E87-A, no. 12, pp. 3309-3317, Dec. 2004.
  16. Y. Wang, D. Gope, V. Jandhyala, and C.-J. R. Shi, "Generalized Kirchoff's current and voltage law formulation for coupled circuit-electromagnetic simulation with surface integral equations," IEEE Trans. on Microwave Theory and Techniques, vol. 52, no. 7, pp. 1673-1682, July 2004. Top download IEEE-MTT paper in 2004 based on IEEE Explorer Statistics
  17. X.-D. Tan and C.-J. R. Shi, "Efficient approximation of symbolic expressions for analog behavioral modeling and analysis," IEEE Trans. on Computer-Aided Design, vol. 23, no. 6, pp. 907-918, June 2004.
  18. X.-D. Tan and C.-J. R. Shi, "Efficient DDD-based interpretable symbolic characterization of large analog circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 12, pp. 3119-3126, Dec. 2003.
  19. X.-D. Tan, C.-J. R. Shi and J.-C. Lee, "Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings," IEEE Trans. on Computer-Aided Design, vol. 22, no. 12, pp. 1678-1684, Dec. 2003.
  20. N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.-J. R. Shi, "IPRAIL: Intellectual property reuse based analog IC layout automation," Integration, the VLSI Journal, vol. 36, no. 4, pp. 237-262, Nov. 2003.
  21. X.-D. Tan and C.-J. R. Shi, "Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis," Integration, the VLSI Journal, vol. 34, no.1-2, pp. 65-86, May 2003.
  22. X.-D. Tan and C.-J. R. Shi, "Efficient VLSI power/ground network sizing based on equivalent circuit modeling," IEEE Trans. on Computer-Aided Design, vol. 22, no. 3, pp. 277-284, March 2003.
  23. V. Jandhyala, Y. Wang, D. Gope, and C.-J. R. Shi, "A surface-based integral equation formulation for coupled electromagnetic and circuit simulation," Microwave Optical Technology Letters, vol. 34, no. 2, pp. 103-106, July 2002.
  24. C.-J. R. Shi and X.-D. Tan, "Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design," IEEE Trans. on Computer-Aided Design, vol. 20, no. 7, pp. 813-827, July 2001.
  25. T. Pi and C.-J. Shi, ``Testability analysis of analog circuits via determinant decision diagrams", IEICE Transactions, vol. E83-A, no. 12, pp. 2608-2613, Dec. 2000.
  26. M. W. Tian and C.-J. Shi, ``Worst-case tolerance analysis of linear analog circuits using sensitivity bands", IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 47, no. 8, pp. 1138-1145, August 2000.
  27. X.-D. Tan and C.-J. Shi, ``Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams", IEEE Trans. Computer-Aided Design, vol. 19, no. 4, pp. 401-412, April 2000.
  28. C.-J. Shi and X.-D. Tan, ``Canonical symbolic analysis of large analog circuits with determinant decision diagrams", IEEE Trans. Computer-Aided Design, vol. 19, no. 1, pp. 1-18, Jan. 2000.
  29. C.-J. Shi and W. H. Kao, ``Guest editorial---special issue on behavioral modeling and simulaiton of mixed-signal/mixed-technology systems", IEEE Trans. Circuits and Systems --- II: Analog and Digital Signal Processing, vol. 46, no. 10, pp. 1261-1261, Oct. 1999.
  30. C.-J. Shi and W. Tian, ``Simulation and sensitivity of linear analog circuits under parameter variations by robust interval analysis", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 4, no. 3, July 1999.
  31. C.-J. Shi and J.A. Brzozowski, ``A characterization of signed hypergraphs and its applications to VLSI via minimization and logic synthesis", Discrete Applied Mathematics, vol. 89, no. 1-3, pp. 223-243, Dec. 1998.
  32. C.-J. Shi, ``Entity overloading for mixed-signal abstraction in VHDL", Journal of Information Science and Engineering,  vol. 14, no.3, pp. 633-644, September 1998.
  33. N. Godambe and C.-J. Shi, ``Behavioral-level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS", Journal of Electronic Testing: Theory and Applications (JETTA), vol. 9, no. 3, August 1998.
  34. C.-J. Shi and J.A. Brzozowski, ``Cluster-cover: A theoretical framework for a class of VLSI-CAD optimization problems", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 3, no. 1, pp. 76-107, Jan. 1998.
  35.  C.-J. Shi, A. Vannelli and J. Vlach, ``Performance-driven layer assignment by integer linear programming and path-constrained hypergraph partitioning", Journal of Heuristics, vol. 3, no. 3, pp. 225-243, November 1997.
  36. C.-J. Shi and J.A. Brzozowski, ``An efficient algorithm for constrained encoding and its applications", IEEE Trans. Computer-Aided Design, vol. 12, no. 12, pp. 1813-1826, Dec. 1993.
  37. C.-J. Shi, ``Analysis, sensitivity and macromodeling of the Elmore delay in linear networks for performance-driven VLSI design", International Journal of Electronics, vol.75, no.3, pp.467-484, Sept. 1993.
  38. C.-J. Shi, A. Vannelli and J. Vlach, ``An improvement on Karmarkar's algorithm for integer programming", COAL Bulletin of the Mathematical Programming Society, vol.21, pp. 23-28, 1992.
  39. C.-J. Shi, ``A signed hypergraph model of constrained via minimization", Microelectronics Journal, vol.23, no.7, pp.533-542, Nov. 1992.
  40. J. Vlach, J. Barby, A. Vannelli, I. Talkhan, and C.-J. Shi, ``Group delay as an estimate of delay in logic", IEEE Trans. Computer-Aided Design, vol.10, no.7, pp. 949-953, July 1991.
  41.  Y. Liu and C.-J. Shi, ``Piecewise delay modeling of MOS VLSI digital circuits", Research & Progress of Solid State Electronics, vol.8, no.4, pp.438-442, 1988.

Conference Papers

  1. L. Zhang, Y. Jiang, and C.-J. R. Shi, "Symmetry-aware placement with transitive closure graphs for analog layout design", Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'08) , Japan, Jan 2008.
  2. L. Zhou, C. Wakayama, R. Panda, N. Jangkrajarng, B. Hu, and C.-J. R. Shi, "Implementing a 2-Gbs 1024-bit ½-rate low-density parity- check code decoder in three-dimensional integrated circuits", invited paper, in Proc. IEEE International Conf. on Computer Design , Lake Tahoe, CA, Oct. 2007.
  3. M. Su, L. Zhou and C.-J. R. Shi, "Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining", in Proc. IEEE International Conf. on Computer Design , Lake Tahoe, CA, Oct. 2007.
  4. W. Chen, G. Shi and C.-J. R. Shi, "A graph-reduction approach to symbolic circuit analysis", Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'07) , Japan, Jan 2007
  5. L. Zhang, and C.-J. Shi, "Template-based parasitic-aware optimization and re-targeting of analog and RF integrated circuit layouts ", IEEE/ACM International Conf. on Computer-Aided design, San Jose, Nov 2006.
  6. B. Hu and C.-J. Shi, "Model compiler driven simulation of multi-technology systems ", Proc. IEEE Symp. Circuits and Systems (ISCAS), May 2006.
  7. Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, and C.-J. Richard Shi, "A high-throughput low-power fully parallel 1024-bit 1/2 rate low density parity check code decoder in 3-dimensional integrated circuits", Asia and South Pacific Design Automation Conf. (ASPDAC'06), Japan, Jan 2006.
  8. *Z. Li and C.-J. R. Shi, "Robust and efficient time-domain circuit simulation by quasi-Newton preconditioned Newton-Krylov iterative methods", Asia and South Pacific Design Automation Conf. (ASPDAC'06), Japan, Jan 2006 (135 out of 432 papers were accepted).
  9. *L. Yang, H. Liu and C.-J. R. Shi, "VLSI implementation of low-error-floor and capacity-approaching performance low-density parity-check codes with multi-rate capacity", IEEE Global Communications Theory Symposium (GLOBECOM), St. Louis, MO, Nov 28-Dec 2, 2005.
  10. B. Hu and C.-J. R. Shi, "Fast-yet-accurate process-voltage-temperature (PVT) simulation by combined direct and iterative methods", IEEE/ACM International Conf. on Computer-Aided Design, Nov. 2005 (acceptance rate: 0.25)
  11. L. Yang, C. Wakayama, and C.-J. R. Shi, "Top-down design of A pi/4 DQPSK transceiver with noise and nonlinearity aware behavioral modeling", IFIP VLSI-Systems-on-Chip Conference, Perth, Australia, Oct. 17-19, 2005.
  12. V. Jandhyala, Y. Kuga, D. Allstot, and C.-J. R. Shi, "Bridging circuits and electromagnetics in a curriculum aimed at microelectronic analog and microwave simulation and design", IEEE Frontier in Education Conf., 2005.
  13. *L. Yang, H. Liu and C.-J. R. Shi, "A cycle elimination method for constructing VLSI-oriented LDPC codes", IEEE 62nd Vehicle Technology Conf., Dallas, TX, USA, September 25 to 28, 2005. (625 out of 1084 accepted).
  14. S. Bhattacharya, N. Jangkrajarng, and C.-J. R. Shi, "Template-driven parasitic-aware optimization of analog integrated circuit layouts", Proc. IEEE/ACM Design Automation Conf., June 2005 (154 out of 735 accepted).
  15. B. Hu, Z. Li, L. Zhou, C.-J. R. Shi, K.-H. Baek, and M.-J. Choe, "Model-compiler based efficient statistical circuit analysis: An industry case study of a 4GHz/6-bit ADC/DAC/DEMUX ASIC", Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'05), Kobe, Japan, May 2005.
  16. L. Yang, C. Wakayama, and C.-J. R. Shi, "Noise-aware behavioral modeling of a fractional-N frequency synthesizer", Proc. Great Lake Symp. on VLSI, April 2005.
  17. Z. Li and C.-J. R. Shi, "An efficiently preconditioned GMRES method for fast parasitic-sensitive deep-submicron VLSI circuit simulation", pp. xxx-xxx in Proc. Design Automation & Test in Europe Conf. (DATE'05), Munich, Germany, March 2005 (Nominated by the Technical Program Committee for Best Paper Award).
  18. *L. Yang, M. Shen, H. Liu and C.-J. R. Shi, ``An FPGA implementation of low-density parity-check code decoder with multi-rate capability", pp. 760-763 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'05), Shanghai, China, Jan. 2005 (177 out of 692 accepted).
  19. R. Hartono, N. Jangkrajarng, S. Bhattacharya, and C.-J. R. Shi, "Automatic device layout generation for analog layout retargeting", pp. 457-462 in Proc. International Conf. on VLSI Design, Jan. 2005.
  20. S. Bhattacharya, N. Jangkrajarng, R. Hartono, and C.-J. R. Shi, "Challenges and techniques for layout automation of radio-frequency integrated circuits", in Proc. Asia Pacific Microwave Conf. (APMC'04), Dec. 2004.
  21. E. Normark, L. Yang, C. Wakayama, P.V. Nikitin, and C.-J. R. Shi, "VHDL-AMS modeling and simulation of a Pi/4 DQPSK transceiver system", pp. 119-124 in Proc. IEEE Behavioral Modeling and Simulation Conf. (BMAS'04), San Jose, CA, Oct. 2004.
  22. B. Wan, E. Acar, S. Nassif, and C.-J. R. Shi, "Design-adaptive device modeling in model compiler for efficient and accurate circuit simulation" pp. 400-405 in Proc. IEEE Behavioral Modeling and Simulation Conf. (BMAS'04), San Jose, CA, Oct. 2004.
  23. B. Wan, P. V. Nikitin, and C.-J. R. Shi, "Circuit level modeling and simulation of mixed-technology systems", pp. 113-116 in Proc. IEEE Systems-on-Chip Conf (SoC'04)., Santa Clara, CA, Sept. 2004.
  24. P. V. Nikitin, E. Normark, C. Wakayama, and C.-J. R. Shi, "VHDL-AMS modeling and simulation of a BPSK transceiver system", Proc. of IEEE International Conf. on Circuits and Systems for Communications, Moscow, Russia, June 2004.
  25. V. Jandhyala, P. Nikitin, J. D. Rockway, J. W. Rockway, N. Champagne, R. Sharpe. D. White, C.-J. R. Shi, and D. Allstot, "Electromagnetic modeling and electromagnetic circuit co-simulation of mixed-signal systems-on-chip", pp. 3281-3284 in Proc. IEEE APS-URSI Symp., Monterey, CA, June 2004.
  26. S. Bhattacharya, N. Jangkrajarng, R. Hartono, C.-J. R. Shi, "Correct-by-construction layout-centric retargeting of large analog designs", pp. 139-144 in Proc. IEEE/ACM Design Automation Conf. (DAC'04), June 2004.
  27. Z. Li and C.-J. R. Shi, ``A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks", pp. 165-168 in Proc. IEEE International Symp. on Circuits and Systems (ISCAS'04), Vancouver Canada, May 2004.
  28. P. Nikitin, V. Jandhyala, D. White, N. Champagne, J. D. Rockway, C.-J. R. Shi, C. Yang, G. Ouyang, Y. Wang, R. Sharpe and J. Rockway, "Modeling and simulation of circuit-electromagnetic effects in electronic design flow," pp. 244-249 in Proc. IEEE 5th International Symp. on Quality Electronic Design (ISQED'04), San Jose. CA, March 2004.
  29. *B. Wan and C.-J. R. Shi, "Hierarchical multi-dimensional table lookup for model compiler based circuit simulation," in Proc. Design, Automation and Test in Europe Conf. (DATE'04), Paris, France, March 2004.
  30. *G. Shi and C.-J. R. Shi, "Parametric reduced ordering modeling for interconnect analysis," pp. 775-780 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04), Japan, Jan. 2004 (148 out of 291 accepted).
  31. *Z. Li, R. Suravarapu, R. Hartono, S. Bhattacharya, K. Mayaram, and C.-J. R. Shi, "CrtSmile: A CAD tool for CMOS RF transistor substrate modeling incorporating layout effects," pp. 163-168 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04), Japan, Jan. 2004 (148 out of 291 accepted).
  32. *S. Bhattacharya, N. Jangkrajarng, R. Hartono, and C.-J. R. Shi, "Hierarchical extraction and verification of symmetry constraints for analog layout automation," pp. 400-405 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04) , Japan, Jan. 2004 (148 out of 291 accepted).
  33. N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.-J. R. Shi, "Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting," pp. 394-399 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'04), Japan, Jan. 2004 (148 out of 291 accepted).
  34. P. Nikitin, W. Lam, and C.-J. R. Shi, "Parametric equivalent circuit extraction for VLSI structures," pp. 198-203 in Proc. IFIP VLSI-SoC Symp., Darmstadt, Germany, Dec. 2003 (46 out of 146 accepted as regular papers).
  35. *L. Yang and C-J. R. Shi, "FROSTY: A fast hierarchy extractor for industrial CMOS circuits," pp. 741-746 in Proc. IEEE International Conf. on Computer-Aided Design (ICCAD'03), Nov. 2003 (130 out of 490 accepted).
  36. *Z. Li and C.-J. R. Shi, "SILCA: Fast-yet-accurate time-domain simulation of VLSI circuits with strong parasitic coupling effects," pp. 793-799 in Proc. IEEE International Conf. on Computer-Aided Design (ICCAD'03), Nov. 2003 (130 out of 490 accepted).
  37. *B. Hu, G. Shi and C.-J. R. Shi, "Symbolic model order reduction," pp. 34-40 in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS'03), San Jose, CA., Oct. 2003 (acceptance rate: 66%).
  38. P. Nikitin, E. Normark, and C.-J. R. Shi, "Coupled electrical-thermal modeling in VHDL-AMS," pp. 128-133 in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS'03), San Jose, CA, Oct. 2003 (acceptance rate: 66%).
  39. Y. Wang, D. Gope, V. Jandhyala, and C.-J. R. Shi, "Integral equation-based coupled electromagnetic circuit simulation in the frequency domain," pp. 328-331 in Proc IEEE International Conf. on Antennas and Propagation, vol. 3, Sept. 2003 (same as C-33).
  40. B. Wan, B. Hu, L. Zhou and C.-J. R. Shi, ``MCAST: An abstract-syntax-tree based model compiler for circuit simulation", pp. 249-252 in Proc. IEEE Custom Integrated Circuits Conf. (CICC'03), San Jose, CA, Sept. 2003 (147 out of 380 papers were accepted).
  41. P. Nikitin and C.-J. R. Shi, "Modeling partial differential equations in VHDL-AMS," pp. 345-348 in Proc. IEEE Application Scientific Integrated Circuits/Systems-on-Chip Conf. (SOC'03), Portland, Oregon, Sept. 2003.
  42. *L. Zhou, H. Bo, B. Wan, and C.-J. R. Shi, ``Rapid BSIM model implementation with VHDL-AMS/Verilog-AMS and MCAST compact model compiler", pp. 285-286 in Proc. IEEE Application Scientific Integrated Circuits/Systems-on-Chip Conf. (SOC'03), Portland, Oregon, Sept. 2003.
  43. Y. Wang, D. Gope, V. Jandhyala and C.-J. R. Shi, "Integral equation-based coupled electromagnetic-circuit simulation in the frequency domain," SRC TechCon Technical Digest, Dallas, August 2003 (Best Paper in Session Award, Mixed Signal Technology Session).
  44. A. Manthe, Z. Li, and C.-J. R. Shi, "Symbolic analysis of analog circuits with hard nonlinearity", pp. 542-545 in Proc. IEEE/ACM Design Automation Conf. (DAC'03), June 2003 (acceptance ratio: 25%).
  45. *S. Bhattacharya and C.-J. R. Shi, "Concurrent gate and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis," pp. 660-663 in Proc. IEEE International Symp. on Circuits and Systems (ISCAS'03), vol. 4, May 2003.
  46. *N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C.-J. R. Shi, "Automatic analog layout resizing for process and performance retargeting," pp. 704-707 in Proc. IEEE International Symp. on Circuits and Systems (ISCAS'03), vol. 4, May 2003.
  47. A. Manthe, Z. Li, C.-J. R. Shi and K. Mayaram, "Symbolic analysis of nonlinear analog circuits," pp. 1108-1109 in Proc. Design, Automation and Test in Europe Conf. (DATE'03), Munich, Germany, March 2003.
  48. *X.-D. Tan and C-.J R. Shi, "Efficient DDD-based term generation algorithm for analog behavioral modeling," pp. 789-794 in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'03), Japan, Jan. 2003.
  49. D. J. Allstot, K. Choi, M. Mar, M. Rubeiz, C.-J. R. Shi and R. Ward, "Parasitic-aware synthesis of RF CMOS power amplifiers via simultaneous topology selection and device sizing," pp. 1242-1247 in Proc. IEEE International Conf. on Communications, Circuits and Systems (ICCCAS'02), June 29-July 2, 2002.
  50. A. Manthe and C.-J. R. Shi, "Finding minimal symbolic expressions for analog modeling", in Proc. IEEE International Conf. on Communications, Circuits and Systems (ICCCAS'02), June 29-July, 2, 2002.
  51. R. Suravarapu, K. Mayaram, and C.-J. R. Shi, "A layout dependent and bias independent scalable substrate model for CMOS RF transistors," pp. 217-220 in Proc. IEEE Radio and Wireless Conf. (RAWCON'2002), Boston, MA, Aug. 2002.
  52. *V. Jandhyala, Y. Wang, D. Gope and C.-J. R. Shi, "Coupled electromagnetic-circuit simulation of arbitrarily-shaped conducting structures using triangular meshes," pp. 38-42 in Proc. IEEE 3rd International Symp. on Quality Electronic Design (ISQED'02), March 2002, San Jose. CA.
  53. *X.-D. Tan and C.-J. R. Shi, "Parametric analog behavioral modeling based on cancellation-free DDDs", Proc. IEEE International Workshop on Behavioral Modeling and Simulation , Santa Rosa, CA, Oct. 2002.
  54. *Y. Wang, V. Jandhyala, and C.-J. R. Shi, "Coupled electromagnetic-circuit simulation of arbitrarily-shaped conducting structures," pp. 233-236 in Proc. IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP'01), Oct. 2001, Boston, MA.
  55. V. Jandhyala, Y. Wang, D. Gope, S. Chakaraborty, and C.-J. R. Shi, "A surface-integral equation-based technique for general coupled circuit-electromagnetic simulation," in Proc. Progress in Electromagnetics Research Symp., Boston, July 2002.
  56. D. Gope, S. Chakraborty, Y. Wang, V. Jandhyala, and C.-J. R. Shi, "A surface-based 3D coupled circuit-electromagnetic simulator with accurate lossy conductor modeling," in Proc. IEEE APS-URSI, San Antonio, June 2002.
  57. A. Manthe and C.-J. R. Shi, ``Lower-bound based DDD minimization for efficient symbolic circuit analysis", pp. 374 - 379 in Proc. IEEE International Conf. on Computer Design (ICCD'91) , Austin TX, Oct. 2001 (Nominated by the program committee for the Best Paper Award).
  58. D. Lungeanu and C.-J. R. Shi, ``Distributed event-driven simulation of VHDL-SPICE mixed-signal circuits", pp 302-307 in Proc. IEEE International Conf. on Computer Design (ICCD'91) , Austin TX, Oct. 2001.
  59. *X.-D. Tan and C.-J. R. Shi, ``Fast power-ground network optimization using equivalent circuit modeling", pp. 550-554 in Proc. 38th IEEE/ACM Design Automation Conf. (DAC'01), Las Vegas, NE, June 2001.
  60. T. Pi and C.-J. R. Shi, ``Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of large analog circuits", pp. 19-22 in Proc. 37th IEEE/ACM Design Automation Conf. (DAC'00), Los Angeles, C.A. June 2000 (154 out of 445 were accepted).
  61. Y. Wang, T. Pi and C.-J. R. Shi, ``Simple-yet-accurate analytic models for deep-submicron VLSI interconnects", Proc. IFIP International Chip Design Automation Conf., Aug. 2000.
  62. D. Lungeanu and C.-J. R. Shi, ``Parallel and distributed VHDL simulation", pp.658-662 in Proc. Design, Automation and Test in Europe (DATE'2000), Paris, France, March 2000 (106 out of 306 were accepted as regular papers).
  63. Y. Bourai and C.-J Shi, ``Layout compaction for yield optimization via critical-area minimization", Proc. Design, Automation and Test in Europe Conference (DATE'00), Paris, France, March 2000.
  64. *T. Pi and C.-J. Shi, ``Analog testability analysis by determinant-decision diagrams-based symbolic analysis", Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 2000.
  65. *X. Tan and C.-J. Shi, ``Symbolic Circuit-Noise Analysis and Modeling with Determinant Decision Diagrams," accepted by Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 2000.
  66. D. Lungeanu and C.-J Shi, ``Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization", accepted by IEEE/ACM International Conference on Computer-Aided Design (ICCAD'99), San Jose, CA, Nov. 1999. (106 out of 317 submissions were selected)
  67. *X. Tan, C.-J. Shi, D. Lungeanu, J.-C. Lee and L.-P. Yuan, ``Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings", pp. in IEEE/ACM 36th Design Automation Conference (DAC'99), New Orleans, LA, June 21-25, 1999. (Best Paper Award.)
  68. *X. Tan and C.-J. Shi, ``Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams", pp. 448-453 in Proc. Design, Automation and Test in Europe (DATE'99), Munich, Germany, Mar. 10-13, 1999.
  69. Y. Bourai and C.-J. Shi, ``Symmetry detection for analog layout recycling", pp. 5-7 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 18-21, 1999.
  70. *X. Tan and C.-J. Shi, ``Balanced multi-level multi-way partitioning of large analog circuits for hierarchical symbolic analysis", pp. 1-4 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, Jan. 18-21, 1999.
  71. C.-J. Shi and W. Tian, ``Automatic test generation for linear(ized) analog circuits under parameter variations", pp. 501-506 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'98), Tokyo, Japan, Feb. 10-13, 1998. (Nominated by the program committee for the Best Paper Award.)
  72. *W. Tian and C.-J. Shi, ``Efficient DC fault simulation of nonlinear analog circuits", pp. 899-904 in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE'98), Paris, France, Feb. 23-26, 1998. (merged EuroDAC and ED&TC conferences.) ( 122 out of 448 submissions were selected)
  73. *X. Tan and C.-J. Shi, ``Hierarchical symbolic analysis of large analog circuits with determinant decision diagrams", pp. 318-321 in Proc. IEEE International Symposium on Circuits and Systems, vol. VI, 1998.
  74. *W. Tian and C.-J. Shi, ``Worst-case analysis of linear analog circuits using sensitivity bands", pp. 110-113 in Proc. IEEE International Symposium on Circuits and Systems, vol. VI, 1998.
  75. *W. Tian and C.-J. Shi, ``Nonlinear Analog DC Fault Simulation by One-Step Relaxation", pp. 126-131 in Proc. 16th IEEE VLSI Test Symposium, Hyatt Regency Monterey, Monterey, CA, April 26-30, 1998. (Best Paper Award.)
  76. *C.-J. Shi and X. Tan, ``Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits", pp. 463-466 in Proc. IEEE Custom Integrated Circuits Conference, San Diego, CA, May 12-14, 1998.
  77. C.-J. Shi, ``Block-level fault isolation using partition theory and logic minimization techniques", pp. 319-324 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'97), Chiba, Japan, Jan. 28-31, 1997.
  78. C.-J. Shi, ``Solving constrained via minimization by compact linear programming", pp. 635-640 in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'97), Chiba, Japan, Jan. 28-31, 1997.
  79. *N. Godambe and C.-J. Shi, ``Behavioral-level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS", pp. 177--183 in Proc. IEEE VLSI Test Symp. (VTS'97), Monterey, CA, April 27 - 30, 1997 (62 out of 178 submissions were accepted).
  80. W. Tian and C.-J. Shi, ``Rapid frequency-domain analog fault simulation under parameter tolerances", pp. 275 -- 280 in Proc. IEEE/ACM Design Automation Conference (DAC'97), Anaheim, CA, June 9-13, 1997 (139 out of 389 submissions accepted).
  81. C.-J. Shi and W. Tian, ``Simulation and sensitivitity of linear(ized) analog circuits under parameter variations", in Proc. 9th IFIP International Conference on Very Large Scale Integration (VLSI'97), Gramado, BRAZIL, August 26-29, 1997.
  82. C.-J. Shi, ``Block-level fault isolation for mixed-signal multichip modules under parameter varations", IEEE/IMAPS MCM Test IV Workshop, Napa Valley, California, Sept. 14 - 17, 1997.
  83. C.-J. Shi, Y. Ye and X. Tan, ``Behavioral model optimization via sensitivity-enhanced genetic search", pp. 17-24 in Proc. IEEE/VIUF International Workshop on Behavioral Modeling and Simulation, Washington DC, Oct. 1997.
  84. *C.-J. Shi and X. Tan, ``Symbolic analysis of large analog circuits with determinant decision diagrams", pp. 366-373 in Proc. IEEE/ACM International Conference on Computer-Aided Design, (ICCAD'97), San Jose, CA, November 9-13, 1997. ( 102 out of 341 submissions were accepted.)
  85. C.-J. Shi, ``Inclusive-OR Boolean satisfiability for via minimization and constrained encoding in VLSI design", Invited Paper in DIMACS Workshop on Satisfiability Problem: Theory and Applications, March 11-13, 1996.
  86. O. Coudert and C.-J. Shi, ``Exact multi-layer topological planar routing", pp. 179-182 in Proc. IEEE Custom Integrated Circuit Conference (CICC'96), San Diego, CA, May 5-8, 1996.
  87. C.-J. Shi, ``Finding a minimal test set for analog fault diagnostic dictionary", pp. 303-308 in Proc. International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability, Beijing, China, July 2-3, 1996.
  88. C.-J. Shi, ``Fault isolation for mixed-signal multichip modules", in IEEE MCM Test II Workshop, Napa Valley, California, Sept. 15 - 18, 1996.
  89. *C.-J. Shi, ``Entity overloading for mixed-signal abstraction in VHDL", pp. 562-567 in Proc. European Design Automation Conference (EuroDAC/EuroVHDL'96), Geneva, Switzerland, September 16-20, 1996. (Nominated by the program committee for the Best Paper Award.)
  90. *C.-J. Shi and N. Godambe, ``Behavioral fault modeling and simulation of phase-locked loops using a VHDL-A like language", pp. 245-250 in Proc. IEEE International ASIC Conference & Exhibit (ASIC'96), Rochester, N.Y., September 23-27, 1996. (Acceptance Ratio: 0.5)
  91. C.-J. Shi, A. Vannelli and J. Vlach, ``Performance-driven layer assignment for printed circuit boards and integrated circuits", pp. 171-174 in Proc. IEEE International ASIC Conference & Exhibit (ASIC'96), Rochester, N.Y., September 23-27, 1996. (Acceptance Ratio: 0.5)
  92. O. Coudert and C.-J. Shi, ``Exact dichotomy-based constrained encoding", pp. 426-431 in Proc. IEEE International Conference on Computer Design (ICCD'96), Austin, Texas, October 7-9, 1996.
  93. *C.-J. Shi and J. A. Brzozowski, ``A framework for the analysis and design of algorithms for a class of VLSI optimization problems", pp. 67-74 in Asia and South Pacific Design Automation Conference (ASP-DAC'95), Aug. 29 - Sept. 1, 1995. (Nominated by the program committee for the Best Paper Award.)
  94. C.-J. Shi, E. Christen, P. Liebmann, S. Krolikoski, and W. Zhou, ``VHDL-A: Analog extension to VHDL", pp. 160-165 in Proc. IEEE International ASIC Conference & Exhibit, Sept. 1994.
  95. *C.-J. Shi and J.A. Brzozowski, ``Efficient constrained encoding for VLSI sequential logic synthesis", pp. 266-271 in Proc. First European Design Automation Conf., Hamburg, Germany, Sep. 1992. (79 papers out of 335 were accepted.)
  96. C.-J. Shi, ``Towards a unified operational semantics for behavior specification of VLSI systems", International Workshop on Computer-Aided Co-Design, Cambridge, Massachusetts, Oct. 7-8, 1993.
  97. *C.-J. Shi, ``A signed hypergraph model of constrained via minimization", pp. 159-166 in Proc. Second Great Lakes Symp. on VLSI, Kalamazoo, MI, Feb. 1992.
  98. *C.-J. Shi and A. Vannelli, ``An improvement on Karmarkar's algorithm for integer programming", in the Sixth SIAM Conference on Discrete Mathematics, Vancouver, June 1992.
  99. C.-J. Shi, ``Modeling k-way splits of physical routings for constrained via minimization", pp. 4B.5.1-4B.5.8 in Proc. 1991 Canadian Conf. on VLSI, Aug. 1991.
  100. *C.-J. Shi, A. Vannelli, and J. Vlach, ``A hypergraph partitioning approach to the via minimization problem", pp. 2.7.1-2.7.8 in Proc. 1990 Canadian Conf. on VLSI, Oct. 1990.
  101. C.-J. Shi and K. Zhang, ``Tree relaxation: a new iterative solution method for linear equations", pp. 2355-2359 in Proc. IEEE Int. Symp. on Circuits and Systems, June 1988.
  102.  C.-J. Shi and K. Zhang, ``A robust approach to timing verification", pp. 56-59 in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD'87), Nov. 1987. (119 papers out of 440 were accepted.)
  103. C.-J. Shi and K. Zhang, ``A newly defined signal delay time and its basic theory", pp. 142-146 in Proc. IEEE Asian Electronics Conference, Hong Kong, September 1987.