Information

• SILCA is targeted for fast yet accurate SPICE-level time-domain simulation of deep-submicron VLSI circuits with strong parasitic coupling effects introduced by interconnect lines, common substrate, power/ground networks, etc.
• Two novel linear-centric techniques are applied in SILCA:
  • Semi-implicit integration predictor and iterative integration corrector are proposed for time-domain discretization.
  • Nonlinear devices are represented by Piecewise Weakly NonLinear (PWNL) models. Therefore, successive variable chord method and low-rank update techniques are applied in nonlinear iteration process.
  With these techniques, SILCA reduces dramatically the number and cost of required LU factorizations.
• More than an order of magnitude speedup over SPICE3 has been observed for circuits with tens of thousands devices, and the efficiency increases further with the size of a circuit.
• SILCA is suitable for accurate time-domain simulation of parasitic-sensitive very large-scale integrated circuits, where the number of linear parasitic devices dominates the number of nonlinear devices.
• SILCA can also be used for mixed-signal circuit analysis and high fidelity coupled circuit and electromagnetic analysis.
• More information:
  • SILCA paper (ICCAD 2003 conference publication)
  • SILCA manual: SILCA is realized based on SPICE3. Therefore, the usage of SILCA is the same as SPICE3. See The Spice Page for information about SPICE3.
  • See the comparison to a coupled iterative/direct method (ISCAS 2004 conference publication)
  • See a recent article about a new BLSN (Big Linear, Small Nonlinear) circuit simulator NSpice-PI for power integrity analysis.

Download

• Will be available soon.

References

• Z. Li and C.-J. R. Shi, "A Coupled Iterative/Direct Method for Efficient Time-Domain Simulaiton of Nonlinear Circuits with Power/Ground Networks", Proc. IEEE Int. Symp. on Circuits and Systems, May 2004, Vancouver, Canada (to appear).pdf
• Z. Li and C.-J. R. Shi, "SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects", Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 793-799, Nov. 2003.pdf
• E. Acar, F. Dartu, and L. T. Pileggi, "TETA: Transistor-Level Waveform Evaluation for Timing Analysis", IEEE Trans. on Computer-Aided Design, vol. 21, no. 5, pp. 605-616, May 2002.
• J. R. Phillips and L. M. Silveira, "Simulation Approaches for Strongly Coupled Interconnect Systems", Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 430-437, November 2001.
• Y. Wang, V. Jandhyala, and C.-J. R. Shi, "Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures", Proc. IEEE Conf. on Electrical Performance of Electronic Packaging, pp. 233-236, October 2001.
• P. F. Cox, R. G. Burch, P. Yang, and D. E. Hocevar, "New Implicit Integration Method for Efficient Latency Exploration in Circuit Simulation", IEEE Trans. on Computer-Aided Design, vol. 8, no. 10, pp. 1051-1064, October 1989.
• W. J. McCalla, Fundamentals of Computer-Aided Circuit Simulation, Kluwer Academic Publishers, 1988.
• T. Fujisawa, E. S. Kuh, and T. Ohtsuki, "A Sparse Matrix Method for Analysis of Piecewise-Linear Resistive Networks", IEEE Trans. on Circuit Theory, vol. CT-19, no. 6, pp. 571-584, November 1972.

Notes

The papers have been made available in PDF format as a courtesy. Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.